The present invention relates to a large scale semiconductor integration circuit, in particular to a semiconductor memory suitable for higher density.
In recent years, densities of semiconductor memories have been made higher and higher. Especially in semiconductor memories comprising dynamic memory cells such as memory cells of single-transistor, single-capacitor type, higher densities have been obtained because the number of elements included in each memory cell is small. The concept of memory array configuration of such a higher-density semiconductor memory is shown in FIG. 2. Memory cells MC (such as MC.sub.11 and MC.sub.12) are arranged at intersections of word lines W.sub.1 -W.sub.m and data lines d.sub.1 -d.sub.n in a matrix form. In this configuration, readout operation is performed as hereafter described. First of all, one word line such as W.sub.1 is selected, whereby signals read out from memory cells connected to this word line appear on data lines d.sub.1 -d.sub.n. Since these signals are typically minute, they are inputted to means for signal sensing SA.sub.1 -SA.sub.n disposed on respective data lines and sensed as pieces (e.g., data bits) of stored information. Thereafter one of these stored information pieces is selected and read out to the outside of the chip. In the case in which the memory cells are memory cells such as single-transistor, single-capacitor memory cells where from stored information is read destructively, the information must be restored. Therefore, the results sensed by the signal sensing means are restored into respective memory cells.
As for refresh operation, signals from the memory cells are first read out onto respective data lines in the same way as the readout operation and sensed by the signal sensing means. The results are restored into respective memory cells, the information stored in the memory cells being refreshed.
As for storing operation as well, signals from the memory cells are first read out onto respective data lines and sensed by the signal sensing means. Thereafter, information pieces inputted from the outside of the chip are selectively stored into desired memory cells by storing means (not illustrated). On the other hand, original stored information pieces are restored into remaining memory cells by using results sensed by the signal sensing means.
Once a certain word line is selected in each operation, signals are thus read out from all memory cells connected to that word line onto respective data lines. The signals must be sensed by the signal sensing means to restore the result. In the configuration of the prior art, therefore, signal sensing means is provided on each data line, or, in a case in which the signal sensing means does not have restoring function, both the signal sensing means and restoring means are provided on each data line. However, the signal sensing means and the restoring means occupy an extremely larger area than that of the memory cells. Further, in recent years, the occupied area has been reduced by providing memory cells with three-dimensional structures. Therefore, the relative occupied area of the signal sensing means and the restoring means has becomes further increased, thereby adversely influencing the development of higher density memories. Further, since the pitch of data lines becomes small, it becomes difficult to make the layout of the signal sensing and restoring means in accordance with that pitch, furthermore. Therefore, there has also been adopted a method whereby the signal sensing means are arranged alternately on both sides of the data line to relax the layout pitch of the signal sensing means as described in 1989 IEEE ISSCC Digest of Technical Papers, pp. 248-249, for example. Although this method is capable of relaxing the layout pitch of the signal sensing means to twice the pitch of the data lines, however, further improvement is impossible.